![]() ![]() After the initial 10-day moisture exposure and subsequent redrying, selected samples were then subjected to moisture cycling to characterize the evolution of the die stresses from cycle to cycle. In addition, the moisture-exposed samples were subsequently baked in a dry atmosphere to drive the moisture back out of the samples and to see whether the effects of moisture absorption were reversible. Both the sample weight gain and transient die stresses were monitored as a function of the exposure time in the high humidity environment. The two types of assembled flip chip packages were exposed to MSL-1 conditions (85/85) in an environmental chamber for various durations from 0 to 240 hours. Both flip chip on laminate and flip chip ceramic ball grid array (CBGA) packaging configurations have been studied. In this study, on-chip piezoresistive sensors were used to perform a variety of measurements of moisture-induced device side die stresses in flip chip packaging. DIP and PBGA), there have been no published studies on the effects of underfill and substrate moisture absorption on the die stress evolution and delamination growth in flip chip assemblies. While the effects of moisture have been examined extensively in plastic encapsulated packages (e.g. Moisture is a significant contributing factor to the failure of microelectronic packaging including phenomena such as popcorn cracking, delaminations, and interfacial fracture. With suitable detail in the models, excellent correlation has been obtained. The measured stress changes due to heat sink clamping where correlated with finite element simulations. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. ![]() After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. ![]() A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. #BUTEL ARC 500 CRACK FREE#The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). ![]() The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |